Semiconductor device and manufacturing method therefor

ABSTRACT

A semiconductor device manufacturing method includes forming a wiring layer, and forming a first insulating film on the wiring layer under a condition that hydrogen in a plasma is 1% or less in all gas components.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2003-063733, filed Mar.10, 2003, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a nonvolatile semiconductordevice and manufacturing method therefor.

[0004] 2. Description of the Related Art

[0005] Nonvolatile memories such as NAND and NOR memories suffer theproblem that a threshold Vth for operating a transistor varies inrepetitive read/write of data. This problem becomes actualized alongwith reduction in the feature size of elements, and readily occurs whenthe film thickness of a gate insulating film is 80 Å or less.

[0006] To solve this problem, a multilayered structure using apassivation film has conventionally been adopted. In this multilayeredstructure, as shown in FIG. 14, a plasma-enhanced-SiON film 51 is formedon an upper metal wiring (e.g., Al-0.5 at % Cu) 50. Aplasma-enhanced-SiN film 52 is formed on the SiON film 51. The SiN film52 is used as a measure against moisture absorption, and the SiON film51 is used to cut off hydrogen contained in the SiN film 52.

[0007]FIG. 15 shows data as a result of a comparison between a shiftamount ΔVth in a structure having a passivation film and a shift amountΔVth in a structure having no passivation film. The structure having apassivation film means a structure in which the SiN film 52 and SiONfilm 51 shown in FIG. 14 are stacked. As shown in FIG. 15, the structurehaving a passivation film exhibits a larger shift amount ΔVth than thestructure having no passivation film.

[0008] The prior art cannot essentially suppress the shift ΔVth in anelement which repeats data read/write even with a multilayered structurehaving a passivation film.

BRIEF SUMMARY OF THE INVENTION

[0009] A semiconductor device manufacturing method according to a firstaspect of the present invention comprises forming a wiring layer, andforming a first insulating film on the wiring layer under a conditionthat hydrogen in a plasma is not more than 1% in all gas components.

[0010] A semiconductor device according to a second aspect of thepresent invention comprises a wiring layer, and a first insulating filmwhich is formed on the wiring layer under a condition that hydrogen in aplasma is not more than 1% in all gas components.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0011]FIG. 1 is a graph showing “01 waveform” according to the firstembodiment of the present invention;

[0012]FIG. 2 is a graph showing the threshold shift amount according tothe first embodiment of the present invention;

[0013]FIG. 3 is a graph showing the dependence of ΔVth on the H₂concentration according to the first embodiment of the presentinvention;

[0014]FIG. 4 is a sectional view showing a semiconductor device havingan SOG film according to the second embodiment of the present invention;

[0015]FIG. 5 is a sectional view showing a semiconductor device having asputtered SiO₂ film according to the third embodiment of the presentinvention;

[0016]FIG. 6 is a sectional view showing a semiconductor device having athermal CVD film according to the third embodiment of the presentinvention;

[0017]FIG. 7 is a sectional view showing a semiconductor device havingan SOG film/HCD-SiN film according to the fourth embodiment of thepresent invention;

[0018]FIG. 8 is a sectional view showing a semiconductor device having aTEOS-O₃-CVD film/HCD-SiN film according to the fourth embodiment of thepresent invention;

[0019]FIGS. 9, 10, 11, 12, and 13 are sectional views, respectively,showing the steps in manufacturing a semiconductor device according tothe fifth embodiment of the present invention;

[0020]FIG. 14 is a sectional view showing a semiconductor device havinga conventional passivation film; and

[0021]FIG. 15 is a table showing the shift amount ΔVth in thepresence/absence of a conventional passivation film.

DETAILED DESCRIPTION OF THE INVENTION

[0022] Preferred embodiments of the present invention will be describedbelow with reference to the several views of the accompanying drawing.In the following description, the same reference numerals denote thesame parts throughout the views of the accompanying drawing.

FIRST EMBODIMENT

[0023] As described above, the prior art cannot essentially suppress theshift ΔVth of the threshold in an element which repeats data read/writeeven with a multilayered structure having a passivation film.

[0024] The primary cause was examined to find out that the hydrogenplasma causes the shift ΔVth. This will be explained in detail withreference to FIGS. 1 to 3.

[0025] To find the cause of the shift ΔVth, “01 waveform” is exemplifiedout of four signal waveforms (00 waveform, 01 waveform, 10 waveform, and11 waveform) in a flash memory. Variations in arbitrary threshold X (seeFIG. 1) at the trailing portion of “01 waveform” are experimented undervarious conditions. The transistor X is selected in “01 waveform”because a threshold at the trailing portion of “01 waveform” variesmost.

[0026] This experiment uses a NAND element. The element is exposed to anatmosphere in which a plasma is generated in hydrogen-containing gas,and degradation in data retention characteristic is checked. At thistime, N₂/H₂ is supplied and an RF plasma is generated in a chamberhaving parallel-plate counter electrodes. A plasma can be formed atH₂/N₂=400/100 sccm, a pressure of about 1 to 1.5 Torr, and an RF powerof 750 W.

[0027]FIG. 2 shows the results of the experiment. On the abscissa ofFIG. 2, “Before W/E” means “before data write/erase”, “After W/E” means“after data write/erase”, and “After Bake 150° C., 2 h” means “afterbaking at 150° C. for 2 h”. Note that “−” on the ordinate of FIG. 2means that the threshold X in FIG. 1 shifts left.

[0028] As shown in FIG. 2, when the element is exposed to the hydrogenplasma as a result of using a hydrogen plasma, reference, a nitrogenplasma, and nitrogen annealing, the shift amount ΔVth of the elementgreatly increases after baking.

[0029]FIG. 3 is a graph showing the relationship between the shiftamount ΔVth in FIG. 2 and the ratio of H₂/N₂. As shown in FIG. 3, theshift amount ΔVth increases for a log(H₂ (%)) of −2 or more. “log(H₂(%))=−2” means that H₂ in the plasma is 1% in all components. That is,exposure of the element to the H₂ plasma generates the shift ΔVth. Atthis time, H₂ in the plasma is 1% or more in all components.

[0030] From this, the shift ΔVth can be suppressed as long as H₂ or SiH₄is 1% or less in all components in a gas plasma containing H such as H₂,SiH₄ (SiH₄ is decomposed into, e.g., H₂ and SiH₂) in formation of aninsulating film, or NH₃. Hence, the above-described degradation in thedata retention characteristic of the element can be prevented by forminga plasma insulating film such as an SiON film at a flow rate ratio atwhich H₂ or SiH₄ is 1% or less with respect to the total gas flow rate.This trend becomes conspicuous when the film thickness of the gateinsulating film of the element is 80 Å or less.

[0031] An insulating film formed under a condition that hydrogen in theplasma is 1% or less in all gas components was examined by SIMS analysisto reveal that the film did not contain any hydrogen. This can also beinvestigated by HFS (Hydrogen Forward Scattering) analysis as long asthe analysis area is about 1 cm² at a film thickness of about 1,000 Å to2,000 Å.

[0032] According to the first embodiment, an element is formed in a stepsuch as LP-CVD (Low Pressure-Chemical Vapor Deposition) or SOG (Spin OnGlass) in which the element is not exposed to a hydrogen-containingplasma. This can suppress variations in threshold Vth for operating atransistor in repetitive data read/write of a nonvolatile memory such asa NAND or NOR memory. The element formed by applying the firstembodiment can improve the Vth shift amount caused by repetitive dataread/write by about 10 times the conventional shift amount.

[0033] The first embodiment is considered to be effective for allnonvolatile memories. That is, the first embodiment can be effectivelyapplied to an element considered to degrade its characteristic uponexposure of the element to hydrogen, such as a ferroelectric memory(FeRAM) having a ferroelectric oxide or a magnetic random access memory(MRAM) having a high-k dielectric tunneling barrier film.

SECOND EMBODIMENT

[0034] In the second embodiment, an insulating film is formed using spincoating (coating film formation) using no plasma.

[0035]FIG. 4 is a sectional view showing a semiconductor deviceaccording to the second embodiment of the present invention. As shown inFIG. 4, a metal wiring (e.g., Al-0.5 at % Cu) 10 is formed on aninsulating film 11. An SOG film 20 is formed as an insulating film onthe metal wiring 10 by spin coating. More specifically, a material suchas polyarylether fluoride, BCB, Cytop, or MSQ is applied by spincoating, and sequentially baked at 80° C. for 1 min, at 200° C. for 1min, and at 450° C. for 30 min.

[0036] According to the second embodiment, the SOG film 20 is formedwithout exposing the element to the H₂ plasma. Similar to the firstembodiment, variations in threshold for operating a transistor can besuppressed.

[0037] The second embodiment uses spin coating to form an insulatingfilm. Even a narrow space between wirings can be filled with theinsulating film without generating any void.

[0038] Film formation by spin coating does not use any plasma, and noelectrostatic damage is applied to a transistor.

THIRD EMBODIMENT

[0039] In the third embodiment, formation of an insulating film bysputtering in the H₂ plasma at 1% or less or by thermal CVD (ChemicalVapor Deposition) using no plasma will be explained.

[0040]FIG. 5 is a sectional view showing a semiconductor deviceaccording to the third embodiment of the present invention. As shown inFIG. 5, a sputtered SiO₂ film 30 is formed as an insulating film on ametal wiring 10 by sputtering in the H₂ plasma at 1 at % or less.

[0041]FIG. 6 is a sectional view showing another semiconductor deviceaccording to the third embodiment of the present invention. As shown inFIG. 6, a thermal CVD film 31 is formed as an insulating film on a metalwiring 10 by thermal CVD. The thermal CVD film 31 can be formed fromTEOS (Tetra Ethyl Ortho Silicate) at 1,100 to 1,500 sccm, O₃ at 4,000 to6,000 sccm, and N₂ at 8,000 to 12,000 sccm at a low temperature of 410°C.

[0042] As the thermal CVD film 31, e.g., an HCD-SiN film can also beformed. The HCD-SiN film can be formed even at a low temperature of 450°C. with the use of HCD (HexaChloroDisilane) because of low activationenergy. The HCD-SiN film is formed by NH₃ reduction at 0.5 to 1 Torr andHCD/NH₃=10 sccm/1,000 sccm.

[0043] According to the third embodiment, the sputtered SiO₂ film 30 orthermal CVD film 31 is formed without exposing the element to the H₂plasma. Similar to the first embodiment, variations in threshold foroperating a transistor can be suppressed.

[0044] Film formation by sputtering can realize low-temperature filmformation. An element can be formed without applying any thermalhysteresis damage to a transistor.

[0045] Film formation by thermal CVD does not use any plasma, and noelectrostatic damage is applied to a transistor.

FOURTH EMBODIMENT

[0046] In the fourth embodiment, insulating films formed in the secondand third embodiments are combined.

[0047]FIG. 7 is a sectional view showing a semiconductor deviceaccording to the fourth embodiment of the present invention. As shown inFIG. 7, an SOG film 20 is formed as a low dielectric constant film (filmhaving a relative dielectric constant of, e.g., 4.0 or less) on a metalwiring 10 by spin coating. After that, an HCD-SiN film 31 a is formed onthe SOG film 20 by thermal CVD.

[0048]FIG. 8 is a sectional view showing another semiconductor deviceaccording to the fourth embodiment of the present invention. As shown inFIG. 8, a TEOS-O₃-CVD film 31 b is formed on a metal wiring 10 bythermal CVD at a low temperature of 410° C. An HCD-SiN film 31 a is thenformed on the TEOS-O₃-CVD film 31 b by thermal CVD.

[0049] According to the fourth embodiment, the SOG film 20, HCD-SiN film31 a, and TEOS-O₃-CVD film 31 b are stacked and formed without exposingthe element to the H₂ plasma. Similar to the first embodiment,variations in threshold for operating a transistor can be suppressed.

[0050] In the fourth embodiment, a passivation film resistant tomoisture can be formed by stacking an insulating film.

[0051] The use of a low dielectric constant SOG film can increase theelement speed.

FIFTH EMBODIMENT

[0052] The fifth embodiment concerns a multilayered structure and methodeffective for a case wherein an insulating film is formed on a wiringand a contact to an upper wiring is formed without exposing an elementto the H₂ plasma, like the above-described embodiments.

[0053] FIGS. 9 to 13 are sectional views, respectively, showing thesteps in manufacturing a semiconductor device according to the fifthembodiment of the present invention.

[0054] As shown in FIG. 9, a metal wiring 10 is formed on an insulatingfilm 11. A first insulating film 41 such as a TEOS film is formed on themetal wiring 10. A second insulating film 42 such as an SOG film orthermal CVD film (e.g., TEOS-O₃-CVD film) is formed on the firstinsulating film 41. An SOG film as the second insulating film 42 isformed by spin coating, or a TEOS-O₃-CVD film is formed by thermal CVD.

[0055] As shown in FIG. 10, the second insulating film 42 is planarizedby CMP (Chemical Mechanical Polish) until part of the upper surface ofthe first insulating film 41 on the metal wiring 10 is exposed.

[0056] As shown in FIG. 11, a third insulating film 43 such as a TEOSfilm is formed on the first and second insulating films 41 and 42.

[0057] As shown in FIG. 12, the second and third insulating films 42 and43 are removed, forming a contact hole 44.

[0058] As shown in FIG. 13, a metal film is formed in the contact hole44, forming a contact 45 which is connected to the metal wiring 10through the first and third insulating films 41 and 43. The contact 45is in contact with the first and third insulating films 41 and 43, butdoes not contact the second insulating film 42.

[0059] According to the fifth embodiment, the first, second, and thirdinsulating films 41, 42, and 43 are formed without exposing the elementto the H₂ plasma. Similar to the first embodiment, variations inthreshold for operating a transistor can be suppressed.

[0060] The SOG film or thermal CVD film (second insulating film) 42 isnot directly formed on the metal wiring 10, but is formed after thefirst insulating film 41 is formed. The SOG film or thermal CVD film(second insulating film) 42 is not exposed in forming the contact hole44. Thus, entrance of moisture into the SOG film or thermal CVD film(second insulating film) 42 can be prevented.

[0061] Additional advantages and modifications will readily occur tothose skilled in the art. Therefore, the invention in its broaderaspects is not limited to the specific details and representativeembodiments shown and described herein. Accordingly, variousmodifications may be made without departing from the spirit or scope ofthe general inventive concept as defined by the appended claims andtheir equivalents.

What is claimed is:
 1. A semiconductor device manufacturing methodcomprising: forming a wiring layer; and forming a first insulating filmon the wiring layer under a condition that hydrogen in a plasma is notmore than 1% in all gas components.
 2. The method according to claim 1,further comprising forming a gate insulating film having a filmthickness of not more than 80 Å.
 3. The method according to claim 1,wherein the first insulating film is formed by spin coating.
 4. Themethod according to claim 1, wherein the first insulating film is formedby sputtering.
 5. The method according to claim 1, wherein the firstinsulating film is formed by thermal CVD.
 6. The method according toclaim 1, further comprising forming a second insulating film on thefirst insulating film under the condition that hydrogen in a plasma isnot more than 1% in all gas components.
 7. The method according to claim6, wherein the first and second insulating films are respectively formedby any of spin coating, sputtering, and thermal CVD.
 8. The methodaccording to claim 4, wherein the first insulating film is formed at notmore than 450° C.
 9. The method according to claim 5, wherein the firstinsulating film is formed at not more than 450° C.
 10. The methodaccording to claim 7, wherein the first and second insulating films areformed at not more than 450° C. in use of thermal CVD or sputtering. 11.The method according to claim 1, further comprising: forming a secondinsulating film on the first insulating film under the condition thathydrogen in a plasma is not more than 1% in all gas components;planarizing the second insulating film until part of an upper surface ofthe first insulating film is exposed; forming a third insulating film onthe part of the upper surface of the first insulating film and thesecond insulating film under the condition that hydrogen in a plasma isnot more than 1% in all gas components; and forming a contact which isconnected to the wiring layer through the first and third insulatingfilms.
 12. The method according to claim 11, wherein the secondinsulating film is formed by spin coating or thermal CVD.
 13. Asemiconductor device comprising: a wiring layer; and a first insulatingfilm which is formed on the wiring layer under a condition that hydrogenin a plasma is not more than 1% in all gas components.
 14. The deviceaccording to claim 13, further comprising a gate insulating film havinga film thickness of not more than 80 Å.
 15. The device according toclaim 13, wherein the first insulating film includes a low dielectricconstant film.
 16. The device according to claim 15, wherein the lowdielectric constant film includes an SOG film.
 17. The device accordingto claim 13, wherein the first insulating film includes a sputtered SiO₂film.
 18. The device according to claim 13, wherein the first insulatingfilm includes a thermal CVD film.
 19. The device according to claim 18,wherein the thermal CVD film includes an HCD-SiN film.
 20. The deviceaccording to claim 13, further comprising a second insulating filmformed on the first insulating film under the condition that hydrogen ina plasma is not more than 1% in all gas components.
 21. The deviceaccording to claim 20, wherein the first and second insulating filmsinclude any of a low dielectric constant film, a sputtered SiO₂ film,and a thermal CVD film.
 22. The device according to claim 13, furthercomprising: a second insulating film which is formed in a selectiveregion on the first insulating film under the condition that hydrogen ina plasma is not more than 1% in all gas components; a third insulatingfilm which is formed on the first and second insulating films under thecondition that hydrogen in a plasma is not more than 1% in all gascomponents; and a contact which is connected to the wiring layer throughthe first and third insulating films and does not contact the secondinsulating film.
 23. The device according to claim 22, wherein thesecond insulating film includes an SOG film or a thermal oxide film. 24.The device according to claim 13, wherein the first insulating filmincludes a film containing no hydrogen.
 25. The device according toclaim 13, wherein the semiconductor device includes a nonvolatilememory.
 26. The device according to claim 13, wherein the semiconductordevice includes a ferromagnetic memory or a magnetic random accessmemory.